1. Field of the Invention
The invention relates to a cascaded diode, and more particularly to a cascaded diode with a deep N-well structure and a method for making the same.
2. Description of the Related Art
In order to constitute a high circuit-integration density and achieve desired functions, a metal-oxide-semiconductor field-effect transistor (MOSFET) with reduced size has been used in the advanced integrated circuit (IC) technology. However, in order to satisfy the requirement of constant field scaling, the level of a power supply voltage is also scaled down in certain IC technology. Hence, computer architectures may require an interface to connect semiconductor chips or sub-systems having different power supply voltages. Owing to the hybrid power supply voltages, the I/O circuit of the interface between chips tends to have the functions of avoiding overstress and/or improper current leakage pathways. The ESD protection circuits are therefore introduced to account for such phenomena.
FIG. 1 shows a block diagram of an integrated circuit having an ESD clamp circuit. Referring to FIG. 1, the conventional integrated circuit 10 includes an input pad 11, an output pad 13, an internal circuit 12, an input pad ESD clamp circuit 14, an output pad ESD clamp circuit 15, and a power rail ESD clamp circuit 16. The ESD clamp circuits 14, 15, and 16 protect the internal circuit 12 from ESD damage. That is, when there are electrostatic charge induced excessive current flowing into the integrated circuit 10 through the pads, the voltage sources VDD, VSS, and the like, the ESD clamp circuits bypasses the electrostatic current without damaging the internal circuit 12.
FIG. 2 shows a power rail ESD clamp circuit using cascaded diodes. As shown in FIG. 2, the power rail ESD clamp circuit 16 is composed of m elemental diodes D1 to Dm. A first power supply voltage VDD is connected to the P terminal of a first elemental diode D1, and a second power supply voltage VSS is connected to the N terminal of the m-th elemental diode Dm. The voltage of the first power supply voltage VDD is higher than that of the second power supply voltage VSS. Each elemental diode has a turn-on voltage, typically 0.8V. A large current is allowed to flow through the elemental diodes when the voltage across the two terminals of the elemental diodes is higher than the turn-on voltage. Therefore, the number of the cascaded diodes may be properly assigned to meet the ESD protection requirement of the clamp circuit.
FIG. 3 shows a structure of a conventional cascaded diode set disclosed in U.S. Pat. No. 6,537,868, entitled “Method for forming novel low leakage current cascaded diode structure”, the content of which is hereby incorporated by reference. The cascaded diode set 16 serves as the ESD clamp circuit. As shown in FIG. 3, the cascaded diode set 16 is formed on a P-type substrate 161 and includes a plurality of elemental diodes. Each elemental diode includes a deep N-well (DNW) 162 formed on the P-type substrate 161, a N-well 163 formed above the deep N-well 162, a heavily doped P-type (P+) region 164 formed in the N-well 163, and a heavily doped N-type (N+) region 165 formed in the N-well 163. As a result of the above depicted structure, a parasitic transistor 166 is formed in each elemental diode, constituted by the heavily doped P-type region 164, the N-well 163 (including the deep N-well 162 and the heavily doped N-type region 165), and the P-type substrate 161.
FIG. 4 shows a circuit of the parasitic transistors in the cascaded diodes of FIG. 2. As is obvious to those of ordinary skill in the art, the cascaded diode set 16 suffers from the leakage current path through the parasitic transistors 166. Although such leakage current may be alleviated by the deep N-well 162, it cannot be effectively reduced.